FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PRAM (Phase Change Random Access Memory) and RRAM (Resistive Random Access Memory) have been developed as next-generation semiconductor memory devices.
FeRAM is disclosed, for example, in Japanese Patent Application Laid-open Publication No. 2000-339973. This type of FeRAM is composed of multiple memory cells arranged in a matrix, and each of the memory cells includes a ferroelectric capacitor and an insulated-gate-type cell transistor. Data are written to, and read from, the ferroelectric capacitors through corresponding bit and word lines respectively which are connected to the insulated-gate-type cell transistors.
Such a type of semiconductor memory device performs a write operation which will be described with reference to FIG. 4 hereafter.
As shown in FIG. 4, voltages of the respective column selecting lines CSL0, CSL1, . . . , CSLn−1 are sequentially raised from a “Low” level to a “High” level. In response, voltages of the respective bit lines /BL0, BL0, /BL1, BL1, . . . , /BLn−1, BLn−1 are raised or dropped. The raised and dropped voltages of the bit lines continue to be written to the memory cells connected to the bit line as data.
As shown in FIG. 5, a ferroelectric film to be used for a ferroelectric capacitor gradually increases its polarization amount over a polarization inversion time. When the polarization inversion time becomes, for example, equal to or longer than approximately 1000 ns, the polarization amount becomes saturated. This polarization property depends on temperature T° C. For this reason, when the ambient temperature around the ferroelectric capacitor becomes higher, the polarization amount accordingly increases. As a result, the polarization amount is smaller in a memory cell when the write time is shorter for the memory cell, while the polarization amount is larger in a memory cell when the write time is longer for the memory cell.
Such a type of memory cell is usually tested in terms of its data retention capability and imprint capability. During these tests, it is likely that a defect-free memory cell may be judged as a defective one because the polarization amount is insufficient, when the time period to write data to the memory cell is too short. In addition, it is likely that a defective memory cell may be judged as a defect-free one because the polarization amount is sufficient, when the time period to write data to the memory cell is too long.
These facts may make it difficult to test the semiconductor memory device accurately in terms of its data retention capability and imprint capability. As a result, it is likely that semiconductor memories each including less reliable memory cells may be shipped out. If a more rigid screening test is applied to semiconductor memory devices, the yield of the semiconductor memory devices may be reduced.